There is a continuing drive to increase the transistor density and circuit performance of integrated circuits in order to further the trend toward increased computer storage and processing capacity with lower costs, size and weight requirements. Engineering has progressed beyond the micron range into the deep sub-micron range, currently into the 28 nm and 20 nm ranges. There is a continuing need for improved efficiency of integrated circuit designs at the sub-micron design range.
In sub-micron integrated circuit design, a contact layer may be used for diffusion (OD) and metal connections. For example, a chip foundry may provide an OD local interconnect layer to improve the source-drain contact resistance and to provide a larger contact area for easier routing. A layer of metal typically referred to as metal-0 (“metal zero” typically denoted as M0) may be formed above the OD layer, typically in the form of metal-0 oxide diffusions (typically denoted as M0OD). In addition, a metal-0 polysilicon layer (typically denoted as M0PO) may be provided above a polysilicon (PO) layer. An integrated circuit layout may include multiple OD layers (typically denoted OD1, OD2, etc.). As a result, there may be multiple metal oxide diffusion layers over multiple OD layers (typically denoted M0OD1, M0OD2, etc.). In addition, there may be multiple metal oxide diffusion layers (M0OD1, M0OD2) over a single OD layer, if desired. Similarly, there may be multiple metal oxide diffusion layers over multiple polysilicon layer regions (typically denoted M0PO1, M0PO2, etc.). Additional metal layers may also be provided (typically denoted as metal-1 or M1, metal-2 or M2 and so forth).
Cross-layer conductors through the transistor stack forming layer connections commonly referred as “vias” are used to provide communication interconnections to the layers of the stack. A conductor with a via connecting to a particular layer is typically referred as a via denoted with the number of that layer. For example, a via to a metal-0 layer is typically referred to as a via-zero (typically denoted as VIA0). A via to an M1 layer is typically denoted as VIA1, a via to an M2 layer is typically denoted as VIA2, etc. A conductor may have multiple vias to connect layers together. For example, a conductor with VIA0 and VIA1 may be used to connect an M1 layer to an M0 layer.
In a conventional sub-micron circuit design, an M0OD1 layer is typically used as an OD contact layer to mitigate strain effects in the source-drain regions of the transistors. A separate M0OD2 layer is typically used as a signal interconnect layer for gating the transistors. In this type of layout, a restriction is imposed on the location of the M0OD2 interconnect layer preventing it from being routed over the OD region (where the M0OD1 layer is located) to avoid signal interference. This forces the M0OD2 control signals to be routed outside of OD region, which leads to area loss, longer routings and associated limitations on transistor density and circuit performance.
There is, therefore, a continuing need for techniques for improving the transistor density and circuit performance of integrated circuits and, more specifically, for improved approaches to control signal routing in sub-micron integrated circuit designs.